A Mixed-Signal VLSI Circuit for Skeletonization by Grassfire Transformation

(1,2)Miklós Oláh, (3)Péter Masa and (1)András Lõrincz
(1)Inst. of Isotopes, Hung. Acad. Sci., Budapest, Hungary
(2)Dept. of Electron Devices, TUB, Budapest
(3)CSEM, Neuchâtel, Switzerland
Grassfire propagation on a square-shape

Contents

  • Abstract
  • Skeletonization by Grassfire Transformation (GT)
  • An ANN model of the GT
  • A Mixed-Signal CMOS VLSI Implementation
  • Circuit Design
  • Processing and Detector Circuit
  • Physical Design
  • Preliminary Circuit Specifications

    • Abstract

    A novel mixed-signal VLSI focal-plane array processor performing the morphological operation of skeletonization of binary images at a processing speed of up to 10K frames/second is presented. The chip directly implements the grassfire algorithm. The system is a 2D array of identical processing elements (PEs) with integrated photodetectors allowing parallel optical input. The skeleton computation is performed in a fully parallel, asynchronous manner by local interactions between PEs, the transformed image is represented by analog values. The transformation is a VLSI analogue of time-integrated off-center-on-surround type nonlinear computation. The output of the transformation can be serially accessed with an on-chip raster-scan circuit generating multiscanning-compatible video signal. The
    system has been designed in a standard 0.7mm digital CMOS process.

    Skeletonization by Grassfire Transformation

     
  • start fire simultaneously along the boundary of the shape and propagate it at constant velocity

    •  
  • determine fire collision points to

    • obtain the skeleton
    Skeleton of a 2D shape

     An ANN model of the GT

  • Architecture:
    • `grassfire' activity (sigma) propagated on neural grid along lateral connections

      •  
    • detector units measure (D) the activity in- and outflow
    Multilayer ANN architecture for GT
  •  Governing equations:
  • Obtaining the skeleton:
  • Features of the resulting skeleton:
  • Simulation flow:

    • A Mixed-Signal CMOS VLSI Implementation

  • lateral connections: current-source like characteristic is feasible in CMOS
  • penalty: anisotropic propagation of `fire'

  • parallel processor array of PEs arranged on a hexagonal grid
  • parallel optical input with integrated photosensors
  • local interaction with digital control signals
  • grassfire and skeleton activation computed and stored with analog signals
  • sequential readout of the original and skeletonized image with on-chip raster-scan circuit

    • Circuit Design

  • function of the stages of the PE

    • Processing and Detector Circuit

  • grassfire activity initialized on capacitor CX (VDD for fire start points, VSS for points where the fire is propagated to); detector activity initialized on capacitor CD as low voltage
  • if VCx>VThreshold,QI1-2, (i.e., it is saturated) the cell sends a switch signal to its neighbours turning on charging current sources (transistors QSC1-6) in the neighbours
  • transferred current is integrated on CX of the neighbour
  • while the cell is saturated and its neighbour is not (logic gates NAND1-6), the copy of current outflow (transistors QSD1-6) is time-integrated on CD of the cell
  • if no current could flow out, CD remains at its initial low voltage representing a skeletal point
  • after saturation of each cell the skeleton is defined as voltage distribution over the CD array

    • Physical Design

  • a 22x26 processor array has been physically designed in a standard 0.7micron digital CMOS process
  • surface covered with the second metal layer (power routing and light shielding)
    •  
     
     
    Grassfire Chip Layout

    Preliminary Circuit Specifications

     
    Function grey-skeleton computation of optical images
    Array size (spatial resolution) 22 columns x 26 rows 
    Computation time (no I/O) 10 usec
    Output bandwidth up to 10 MHz
    Power supply 5V
    Power dissipation 0.1W
    Technology ES2 ecpd07 dual-metal single-poly CMOS
    Chip size 21 sqmm
    Imaging area 3 mm x 3.1 mm
    Number of transistors in the core area 68 500
     Last updated on 13th January, 1998. Created by Miklós Oláh